In IC designs, computer simulation processes are used to check integrity of the design and predict a manufacturability of a resulting circuit. As semiconductor technology is moving to smaller technology nodes, process latitude, due to decreasing lithography tool focus margin, is of increasing importance in a manufacturability of a resulting device. Tool focus fluctuation has an impact on resist pattern shape, which not only changes wafer CD, but also decreases pattern height. It is implicit that the resist loss influences pattern formation after etching, and resist loss is important for process control. However, some traditional processes may utilize a two-dimensional tool that fails to account for process latitude. Some three-dimensional models, such as AFM or cross-sectional SEM, may be configured to account for a process latitude, but are computationally intensive and require a highly skilled engineer, resulting in a very long turnaround time. As such, three-dimensional models are frequently utilized off-line and after a mask writing step.
A need therefore exists for methodology and an apparatus enabling a simulation process to check integrity of the design and predict a manufacturability of a resulting circuit that accounts for process latitude without a long turnaround time and a highly skilled engineer.